Journal cover / Nanoscale / Volume 18, Issue 32
https://pubs.rsc.org/nr/issue/18/32
Abstract
Scalable batch-type synthesis of layered 2D-SnS2 transistors integration enabled by BEOL-compatible low-thermal budget processes
Two-dimensional (2D) semiconductors have been widely explored for next-generation electronics, with rapid progress in both large-area synthesis and device integration. However, bridging these advances toward practical semiconductor processing requires batch-level uniformity and wafer-to-wafer reproducibility under a low thermal budget compatible with back-end-of-line (BEOL) integration, which remain insufficiently addressed. Here, we demonstrate a BEOL-compatible, batch-type synthesis of layered 2D-SnS2 at 350 °C and its scalable transistor integration. The sulfurization-based low-temperature conversion technique yields 2H-stacked multilayer SnS2 with a bandgap of ∼2.3 eV and a high work function of ∼5.9 eV. Wafer- and batch-level uniformity are systematically evaluated by Raman spectroscopy and atomic force microscopy (AFM), showing tightly distributed A1g peak positions and minimal thickness variation over 4-inch full wafers (400 measurement points) and across multiple wafers processed in the same run. Statistical analysis of 200 transistors fabricated across ten wafers reveals tightly distributed switching characteristics, with a batch-averaged on/off ratio of (2.95 ± 0.94) × 105, a threshold voltage of 5.22 ± 0.64 V, and an extrinsic field-effect mobility of 0.0367 ± 0.0045 cm2 V−1 s−1. This work provides a practical pathway toward BEOL-compatible low-thermal budget batch processing and transistor integration of 2D semiconductors.
